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  general description the MAX5074 isolated pwm power ic features integrated switching power mosfets connected in a voltage- clamped, two-transistor, power-circuit configuration. this device can be used in both forward and flyback configu- rations with a wide input voltage range from 11v to 76v and up to 15w of output power. the voltage-clamped power topology enables full recovery of stored magnetizing and leakage inductive energy for enhanced efficiency and reliability. a look- ahead signal for driving secondary-side synchronous rectifiers can be used to increase efficiency. a wide array of protection features includes uvlo, overtemperature shutdown, and short-circuit protection with hiccup current limit for enhanced performance and reliability. operation up to 500khz allows smaller exter- nal magnetics and capacitors. the MAX5074 is rated for operation over the -40? to +125? temperature range and is available in a 20-pin tssop package. warning: the MAX5074 is designed to work with high voltages. exercise caution. applications ieee 802.3af pd power supplies isolated ip phone power supplies high-efficiency telecom/datacom power supplies 48v input, isolated power-supply modules wlan access-point power supplies adsl line cards adsl line-driver power supplies distributed power systems with 48v bus features ? clamped, two-switch power ic for high efficiency ? no reset winding required ? up to 15w output power ? bias voltage regulator with automatic high- voltage supply turn-off ? 11v to 76v wide input voltage range ? integrated high-voltage 0.4 ? power mosfets ? feed-forward voltage-mode control for fast input transient rejection ? programmable brownout undervoltage lockout ? internal overtemperature shutdown ? indefinite short-circuit protection with programmable fault integration ? integrated look-ahead signal for secondary-side synchronous rectification ? >90% efficiency with synchronous rectification ? up to 500khz switching frequency ? high-power (1.74w), small-footprint 20-pin thermally enhanced tssop package MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications ________________________________________________________________ maxim integrated products 1 20 19 18 17 16 15 14 13 1 2 3 4 5 6 7 8 inbias hvin uvlo bst rcff fltint rtct regout top view drnh xfrmrh drvin xfrmrl ppwm css opto ramp 12 11 9 10 src pgnd cs gnd MAX5074 tssop pin configuration ordering information MAX5074 drnh src drvl drvh qh ql d2 d1 d3 t1 v in c in c out v out xfrmrh xfrmrl simplified application circuit 19-3312; rev 0; 7/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. * ep = exposed pad. evaluation kit available part temp range pin-package MAX5074aup -40 c to +125 c 20-tssop-ep*
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v hvin = 12v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. hvin, inbias, drnh, xfrmrh, xfrmrl to gnd.................................................-0.3v to +80v bst to gnd ............................................................-0.3v to +95v bst to xfrmrh .....................................................-0.3v to +12v pgnd to gnd .......................................................-0.3v to +0.3v uvlo, ramp, css, opto, fltint, rcff, rtct to gnd......................................................-0.3v to +12v src, cs to gnd.......................................................-0.3v to +6v regout, drvin to gnd .......................................-0.3v to +12v regout to hvin ...................................................-80v to +0.3v regout to inbias ................................................-80v to +0.3v regout current ................................................................50ma ppwm to gnd....................................-0.3v to (regout + 0.3v) ppwm current .................................................................?0ma drnh, xfrmrh, xrfmrl, src continuous current (average) t j = +125?......................................................................0.9a t j = +150?......................................................................0.6a continuous power dissipation (t a = +70?) 20-pin tssop-ep (derate 21.7mw/? above +70?) ....1.739w 20-pin tssop-ep ( ja ) ................................................46?/w operating temperature range .........................-40? to +125? maximum junction temperature .....................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? parameter symbol conditions min typ max units input supply range v hvin 11 76 v oscillator (rtct) pwm frequency f s r rtct = 25k ? , c rtct = 100pf 256 khz maximum pwm duty cycle d max r rtct = 25k ? , c rtct = 100pf 47 % maximum rtct frequency f rtctmax (note 2) 1 mhz rtct peak trip level v th 0.51 x v regout v rtct valley trip level 0.04 x v regout v rtct input bias current ? ? rtct discharge mosfet r ds(on) sinking 20ma 30 60 ? rtct discharge pulse width 50 ns look-ahead logic (ppwm) ppwm to xfrmrl output propagation delay t ppwm ppwm rising to xfrmrl falling 110 ns ppwm output high v oh sourcing 2ma 7.0 11.0 v ppwm output low v ol sinking 2ma 0.4 v pwm comparator (opto, ramp, rcff) common-mode range v cm-pwm 0 5.5 v input offset voltage 10 mv input bias current -2 +2 ? ramp to xfrmrl propagation delay from ramp (50mv overdrive) rising to xfrmrl rising 100 ns minimum opto voltage v css = 0v, opto sinking 2ma 1.47 v minimum rcff voltage rcff sinking 2ma 2.18 v
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications _______________________________________________________________________________________ 3 electrical characteristics (continued) (v hvin = 12v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units regout ldo (regout) inbias floating, v hvin = 11v to 76v 8.3 9.2 regout voltage set point v regout v inbias = v hvin = 11v to 76v 9.5 11.0 v inbias floating, v hvin = 15v, i regout = 0 to 30ma 0.25 regout load regulation v inbias = v hvin = 15v, i regout = 0 to 30ma 0.25 v inbias floating, i regout = 30ma 1.25 regout dropout voltage v inbias = v hvin , i regout = 30ma 1.25 v regout undervoltage lockout threshold regout rising 6.6 7.4 v regout undervoltage lockout threshold hysteresis regout falling 0.7 v soft-start (css) soft-start current i css 33 ? integrating fault protection (fltint) fltint source current i fltint 80 ? fltint trip point fltint rising 2.7 v fltint hysteresis 0.8 v internal power mosfets (see figure 1, qh and ql) on-resistance r ds ( on ) v drvin = v bst = 9v, v xfrmrh = v src = 0v, i ds = 50ma 0.4 0.8 ? off-state leakage current -5 +5 ? total gate charge per fet 15 nc high-side driver low-to-high delay driver delay until fet v gs reaches 0.9 x (v bst - v xfrmrh ) and is fully on 80 ns high-to-low delay driver delay until fet v gs reaches 0.1 x (v bst - v xfrmrh ) and is fully off 40 ns driver output voltage bst to xfrmrh with high side on 8 v low-side driver low-to-high delay driver delay until fet v gs reaches 0.9 x v drvin and is fully on 80 ns high-to-low delay driver delay until fet v gs reaches 0.1 x v drvin and is fully off 40 ns current-limit comparator (cs) current-limit threshold voltage v ilim 140 156 172 mv current-limit input bias current i bilim 0 < v cs < 0.3v -2 +2 ?
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 4 _______________________________________________________________________________________ electrical characteristics (continued) (v hvin = 12v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) (note 1) parameter symbol conditions min typ max units propagation delay to xfrmrl t dilim from cs rising (10mv overdrive) to xfrmrl rising 160 ns boost voltage circuit (see figure 1, qb) driver output delay t ppwmd 200 ns one-shot pulse width t pwqb 300 ns qb r ds(on) sinking 20ma 30 60 ? thermal shutdown shutdown temperature t sh temperature rising +160 c thermal hysteresis t hyst 15 c undervoltage lockout (uvlo) uvlo threshold v uvlo v uvlo rising 1.14 1.38 v uvlo hysteresis v hyst 140 mv uvlo input bias current i buvlo v uvlo = 3v -100 +100 na supply current from v hvin = 11v to 76v, v css = 0v, v inbias = 11v 0.7 2 from v inbias = 11v to 76v, v css = 0v, v hvin = 76v 4.4 6.0 supply current from v hvin = 76v 7 ma standby supply current v uvlo = 0v 1 ma note 1: all limits at -40? are guaranteed by design and not production tested. note 2: output switching frequency is half of oscillator frequency. undervoltage lockout threshold vs. temperature MAX5074 toc01 temperature ( c) v uvlo (v) 110 95 -25 -10 5 35 50 65 20 80 1.2425 1.2450 1.2475 1.2500 1.2525 1.2550 1.2575 1.2600 1.2400 -40 125 uvlo rising standby current vs. temperature MAX5074 toc02 temperature ( c) standby current ( a) 110 95 65 80 -10 5 20 35 50 -25 35 70 105 140 175 210 245 280 315 350 0 -40 125 i hvin v uvlo = 0v hvin input current vs. temperature MAX5074 toc03 temperature ( c) i hvin (ma) 110 95 -25 -10 5 35 50 65 20 80 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.0 -40 125 v hvin = 76v inbias floating regout = drvin typical operating characteristics (v hvin = 48v, v inbias = 15v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.)
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications _______________________________________________________________________________________ 5 regout voltage vs. temperature MAX5074 toc04 temperature ( c) v regout (v) 110 95 -25 -10 5 35 50 65 20 80 8.625 8.650 8.675 8.700 8.725 8.750 8.775 8.800 8.600 -40 125 v hvin = 76v inbias floating regout voltage vs. input voltage MAX5074 toc05 v hvin (v) v regout (v) 63 50 37 24 8.67 8.69 8.71 8.73 8.75 8.65 11 76 inbias floating regout uvlo voltage vs. temperature MAX5074 toc06 temperature ( c) regout uvlo voltage (v) 110 95 80 65 50 35 20 5 -10 -25 6.25 6.50 6.75 7.00 7.25 7.50 6.00 -40 125 rising falling regout voltage vs. load current MAX5074 toc07 i regout (ma) v regout (v) 25 20 15 10 5 8.60 8.65 8.70 8.75 8.55 030 v hvin = 15v inbias floating hvin and inbias input current vs. temperature MAX5074 toc08 temperature ( c) i hvin (ma) 110 95 65 80 -10 5 20 35 50 -25 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 -40 125 i inbias v hvin = v inbias = 76v i hvin v hvin = v inbias = 76v regout voltage vs. temperature MAX5074 toc09 temperature ( c) v regout (v) 110 95 65 80 -10 5 20 35 50 -25 10.51 10.52 10.53 10.54 10.55 10.56 10.57 10.58 10.59 10.60 10.50 -40 125 v hvin = v inbias = 76v regout voltage vs. input voltage MAX5074 toc10 v hvin (v) v regout (v) 63 50 37 24 10.52 10.54 10.56 10.58 10.60 10.50 11 76 hvin = inbias regout voltage vs. load current MAX5074 toc11 i regout (ma) v regout (v) 25 20 15 10 5 10.45 10.50 10.55 10.60 10.40 030 v hvin = v inbias = 15v typical operating characteristics (continued) (v hvin = 48v, v inbias = 15v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.)
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 6 _______________________________________________________________________________________ typical operating characteristics (continued) (v hvin = 48v, v inbias = 15v, c inbias = 1?, c regout = 2.2?, r rtct = 25k ? , c rtct = 100pf, c bst = 0.22?, v css = v cs = 0v, v ramp = v uvlo = 3v, t a = t j = -40? to +125?, unless otherwise noted. typical values are at t a = +25?, unless otherwise noted.) operating frequency vs. temperature MAX5074 toc12 temperature ( c) operating frequency (khz) 110 95 -25 -10 5 35 50 65 20 80 250 300 350 400 450 500 550 600 200 -40 125 r rtct = 12k ? c rtct = 100pf r rtct = 25k ? c rtct = 100pf soft-start current vs. temperature MAX5074 toc13 temperature ( c) soft-start current ( a) 110 95 -25 -10 5 35 50 65 20 80 31.25 31.50 31.75 32.00 32.25 32.50 32.75 33.00 31.00 -40 125 minimum rcff and opto levels vs. temperature MAX5074 toc14 temperature ( c) v rcff (v), v opto (v) 110 95 -25 -10 5 35 50 65 20 80 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 1.00 -40 125 opto rcff current-limit comparator threshold vs. temperature MAX5074 toc15 temperature ( c) v regout (mv) 110 95 65 80 -10 5 20 35 50 -25 151 152 153 154 155 156 157 158 159 160 150 -40 125 hvin rising ppwm to xfrmrl skew vs. temperature MAX5074 toc16 temperature ( c) ppwm to xfrml skew (ns) 110 95 65 80 -10 5 20 35 50 -25 106 107 108 109 110 111 112 113 114 115 105 -40 125 fltint current vs. temperature MAX5074 toc17 temperature ( c) i fltint ( a) 110 95 65 80 -10 5 20 35 50 -25 76 77 78 79 80 81 82 83 84 85 75 -40 125 fltint shutdown voltage vs. temperature MAX5074 toc18 temperature ( c) v fltint (v) 110 95 65 80 -10 5 20 35 50 -25 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 1.8 -40 125 falling rising power mosfets r ds(on) vs. temperature MAX5074 toc19 temperature ( c) r ds(on) ( ? ) 110 95 65 80 -10 5 20 35 50 -25 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.20 -40 125
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications _______________________________________________________________________________________ 7 pin description pin name function 1 regout regulator output. always present as long as hvin is powered with a voltage above uvlo threshold. bypass regout to gnd with a minimum 2.2? ceramic capacitor. 2 rtct oscillator frequency set input. connect a resistor from rtct to regout and a capacitor from rtct to gnd to set the oscillator frequency. 3 fltint fault integration input. during persistent current-limit faults, a capacitor connected to fltint is charged with an internal 80? current source. switching is terminated when v fltint reaches 2.7v. an external resistor connected in parallel discharges the capacitor. switching resumes when v fltint drops to 1.9v. 4 rcff feed-forward input. to generate the pwm ramp, connect a resistor from rcff to hvin and a capacitor from rcff to gnd. 5 ramp pwm ramp sense input. connect ramp to rcff. 6 opto pwm comparator inverting input. connect the collector of the optotransistor to opto and a pullup resistor to regout. 7 css soft-start and reference. connect a 10nf or greater capacitor from css to gnd. 8 ppwm pwm pulse output. ppwm leads the internal power mosfet pulse by approximately 100ns. 9 gnd signal ground. connect gnd to pgnd. 10 cs current-sense input. the current-limit threshold is internally set to 156mv relative to pgnd. the device has an internal noise filter. if necessary, connect an external rc filter for additional filtering. 11 pgnd power ground. connect pgnd to gnd. 12 src internal low-side power mosfet source. connect src to pgnd with a low-value resistor for current limiting. 13 xfrmrl low-side connection for the isolation transformer 14 drvin mosfet gate-driver supply input. bypass drvin with at least 0.1? to pgnd. connect drvin to regout. 15 xfrmrh high-side connection for the isolation transformer 16 drnh drain connection of the internal high-side pwm power mosfet. connect drnh to the most positive rail of the input supply. bypass drnh appropriately to handle the heavy switching current through the transformer. 17 bst boost input. bst is the boost connection point for the high-side mosfet driver. connect a minimum 0.1? capacitor from bst to xfrmrh with short and wide pc board traces. 18 uvlo undervoltage lockout input. connect a resistive divider from hvin to uvlo and from uvlo to gnd to set the uvlo threshold. 19 hvin high-voltage input. connect hvin to the most positive input supply rail. 20 inbias input from the rectified bias winding. inbias is an input to the internal linear voltage regulator (regout). ?p exposed paddle. ep is internally connected to gnd. connect the exposed paddle to a copper pad to improve power dissipation.
MAX5074 detailed description the MAX5074 pwm power ic is the primary-side controller for voltage-mode, isolated forward or flyback power converters. this device provides a high degree of integration aimed at reducing the cost and printed circuit board area of isolated output power supplies. use the MAX5074 primarily in 48v power bus applications. the MAX5074 is a complete power ic capable of deliver- ing up to 15w of output power. this device contains pwm circuitry and integrated power mosfets. figure 1 shows the MAX5074? block diagram. the MAX5074 includes undervoltage lockout, overtemperature shutdown, and short-circuit protection for enhanced performance and reliability. operation up to 500khz allows the use of small external magnetics and capacitors. power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 8 _______________________________________________________________________________________ ovt uvlo refok regok ovrld t t 5v 5v 80 a 33 a iflt 5v ovrld cpwm ilim cuvlo 1 4 regout rcff 3 5 6 fltint ramp opto 7 9 css gnd 20 19 18 8 17 inbias hvin uvlo ppwm bst 15 xfrmrh 14 drvin 13 xfrmrl 16 drnh 12 src 11 pgnd 2 rtct 10 cs regok reg ovt refok ref (1.25v) 7.5v 50 ? gnd q d r q r t-ff shdn osc 50 ? gnd r s q clk thermal shutdown ovt 1.25v uvlo 80ns delay leading- edge delay one shot level shift 10mhz pgnd 150mv qh qb ql 0.4 ? 30 ? 0.4 ? MAX5074 2.7v/1.9v figure 1. block diagram
power topology the two-switch forward converter topology offers out- standing robustness against faults and transformer saturation while affording efficient use of the integrated 0.4 ? power mosfets. voltage-mode control with feed-forward compensation allows the rejection of input supply disturbances within a single cycle similar to that of current-mode controlled topologies. the two-switch power topology recovers energy stored in both the magnetizing and the parasitic leakage inductances of the transformer. the typical application circuit , forward converter (figure 3) shows the schematic diagram of a 48v input and 5v, 3a output isolated power supply. figure 4 shows the schematic diagram of a flyback converter using the MAX5074. undervoltage lockout (uvlo) the uvlo block monitors the input voltage hvin through an external resistive divider (r24 and r25) connected to uvlo (see figure 3). use the following equation to calculate r24 and r25: where v uvloin is the desired input voltage lockout level and v uvlo is the undervoltage lockout threshold (1.25v, typ). internal regulators as soon as power is provided to hvin, internal power supplies power the uvlo detection circuitry. regout is used to drive the internal power mosfets. bypass regout with a minimum 2.2? ceramic capacitor. the hvin ldo steps down v hvin to a nominal output voltage (regout) of 8.75v. a second parallel ldo powers regout from inbias. a tertiary winding connected through a diode to inbias powers up regout once switching commences. this will bring regout to 10.5v (typ) and shut off the current flowing from hvin to regout. this results in a lower on-chip power dissipa- tion and higher efficiency. soft-start program the MAX5074 soft-start with an external capaci- tor between css and gnd. when the device turns on, the soft-start capacitor (c css ) charges with a constant current of 33?, ramping up to 7.3v. during this time, the feedback pin (opto) is clamped to v css + 0.6v. this initially holds the duty cycle lower than the value the regulator tries to impose, thus preventing voltage overshoot at the output. when the MAX5074 turns off, the soft-start capacitor internally discharges to gnd. secondary-side synchronization the MAX5074 provides convenient synchronization for optional secondary-side synchronous rectifiers. figure 2 shows the connection diagram with a high-speed opto- coupler. choose an optocoupler with a propagation delay of less than 80ns. the synchronizing pulse is generated approximately 110ns ahead of the main pulse that drives the two power mosfets. voltage-mode control and the pwm ramp for voltage-mode control, the feed-forward pwm ramp is generated at rcff. from rcff, connect a capacitor to gnd and a resistor to hvin. the ramp generated is applied to the noninverting input of the pwm comparator at ramp and has a minimum voltage of approximately 2v. the slope of the ramp is determined by the voltage at hvin and affects the overall loop gain. the ramp peak must remain below the dynamic range of rcff of 5.5v. assuming the maximum duty cycle approaches 50% at a minimum input voltage (pwm uvlo turn-on threshold), use the following formula to calculate the minimum value of either the ramp capacitor or resistor: where f s is the switching frequency, v r(p-p) is the peak-to-peak ramp voltage (2v, typ). rc v fv rcff rcff uvloin srpp ? 2 () vv r r uvloin uvlo =+ ? ? ? ? ? ? 1 24 25 MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications _______________________________________________________________________________________ 9 ps9715 or equivalent high-speed optocoupler c 5v r MAX5074 u1 ppwm pgnd u2 figure 2. secondary-side synchronous rectifier driver using a high-speed optocoupler
MAX5074 maximize the signal-to-noise ratio by setting the ramp peak as high as possible. calculate the low-frequency, small-signal gain of the power stage (the gain from the inverting input of the pwm comparator to the output) using the following formula: g ps = n sp xr rcff xc rcff xf s where n sp is the secondary to primary power trans- former turns ratio. oscillator the MAX5074 oscillator is externally programmable through a resistor connected from rtct to regout and a capacitor connected from rtct to gnd. the pwm frequency will be 1/2 the frequency at rtct with a 50% duty cycle. use the following formula to calculate the oscillator components: where c pcb is the stray capacitance on the pc board (14pf, typ), v th is the rtct peak trip level, and f s is the switching frequency. integrating fault protection the integrating fault protection feature allows the MAX5074 to ignore transient overcurrent conditions for a programmable amount of time, giving the power supply time to behave like a current source to the load. this can happen, for example, under load-current transients when the control loop requests maximum current to keep the output voltage from going out of regulation. program the ignore time externally by connecting a capacitor to fltint. under sustained overcurrent faults, the voltage across this capacitor ramps up toward the fltint shut- down threshold (typically 2.7v). when fltint reaches the threshold, the power supply shuts down. a high- value bleed resistor connected in parallel with the fltint capacitor allows the capacitor to discharge toward the restart threshold (typically 1.9v). crossing the restart threshold soft-starts the supply again. the ilim comparator provides cycle-by-cycle current limiting with a typical threshold of 156mv. the fault inte- gration circuit works by forcing an 80? current into fltint for one clock every time the current-limit com- parator ilim (figure 1) trips. use the following formula to calculate the approximate capacitor needed for the desired shutdown time: where i fltint is typically 80?, and t sh is the desired ignore time during which current-limit events from the current-limit comparator are ignored. this is an approximate formula; some testing may be required to fine tune the actual value of the capacitor. calculate the approximate bleed resistor needed for the desired recovery time using the following formula: where t rt is the desired recovery time. choose at least t rt = 10 x t sh . typical values for t sh range from a few hundred microseconds to a few mil- liseconds. shutdown shut down the MAX5074 by driving uvlo to gnd using an open-collector or open-drain transistor con- nected to gnd. the ic will be internally shut down if regout is below its uvlo level. the MAX5074 also features internal thermal shutdown using a temperature sensor that monitors the high-power area. a thermal fault arises from excessive dissipation in the power mosfets or in the regulator. when the temperature limit is reached (+160?), the temperature sensor ter- minates switching and shuts down the regulator. the integration of thermal shutdown and the power mosfets results in a very robust power circuit. applications information isolated telecom power supply figure 3 shows a typical application circuit of an isolat- ed power supply with a 30v to 60v input. this power supply is fully protected and can sustain a continuous short circuit at its output terminals. r t c fltint rt fltint ? ? ? ? ? ? ? ln . . 27 19 c it fltint fltint sh ? 14 . r fc c v vv rtct s rtct pcb regout regout th ? + ? ? ? ? ? ? ? 1 2( )ln power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 10 ______________________________________________________________________________________
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications ______________________________________________________________________________________ 11 rtct src css gnd opto pgnd cs bst xfrmrh xfrmrl inbias MAX5074 uvlo fltint drvin regout rcff ramp hvin drnh ppwm r25 r24 r13 c12 c13 c9 r12 c1 u1 pgnd vin+ r21 r15 c14 c11 r22 c20 r23 r10 pgnd c7 c8 r6 c6 d1 d2 d5 r9 t1 c15 u2 fod2712 e c led fb comp gnd c19 c10 r3 r1 r2 d3 l1 c17 c18 sgnd v out d4 figure 3. typical application circuit (48v power supply, evaluation kit available)
MAX5074 chip information transistor count: 7043 process: bicmos power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications 12 ______________________________________________________________________________________ rtct src css gnd opto pgnd cs bst xfrmrh xfrmrl inbias MAX5074 uvlo fltint drvin regout rcff ramp hvin drnh ppwm r25 r24 r13 c12 c13 c9 r12 c1 u1 pgnd vin+ r21 r15 c14 c11 r22 c20 r23 r10 pgnd c7 c8 r6 c6 d1 d2 d3 r9 t1 c15 u2 fod2712 e c led fb comp gnd c19 r3 r1 r2 d4 c17 c11 sgnd v out figure 4. for lower power applications, the MAX5074 can be used in a flyback converter configuration. this eliminates the need for an output inductor and simplifies the design of multiple output power supplies.
MAX5074 power ic with integrated mosfets for isolated ieee 802.3af pd and telecom power-supply applications maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 13 2004 maxim integrated products printed usa is a registered trademark of maxim integrated products. package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation go to www.maxim-ic.com/packages .) tssop 4.4mm body.eps d 1 1 21-0108 package outline, tssop, 4.40 mm body exposed pad


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